Hardware verification · thermodynamic sampling

p-bit Sampler Core — Verification Workbench

A deterministic, bit-accurate golden reference model for a probabilistic-bit sampler datapath — with a full chain of custody. Configure the hardware, sample against the exact Boltzmann distribution, inspect every number, download the receipt, and score a device's own sample stream for pass/fail. All computed live in your browser.

RTL bit-exact 12,864 / 12,864 Icarus Verilog PASS reference: exact Boltzmann engine: seeded · reproducible
A Datapath configuration
8
Qm.n field accumulator width (the MAC datapath).
6
ROM = 26 entries × 12-bit output.
16
Maximal-length Galois LFSR, scattered per-site seeds.
1.00
Deterministic: same seed → identical result. This is the audit anchor.
datapath bit-cost
—
B Sample & score vs exact Boltzmann
✓Samples correctly
Total-variation distance
0.000
KL( sampled ‖ exact )
0.000
exact Boltzmann P(state) hardware-model samples lower strip = residual (sampled − exact) per state
Field MAC
Q_.8
hᵢ+ΣJ s
× 2β
temperature
scale to z
Sigmoid LUT
2^6 x 12b
p=σ(z)
Stochastic cmp
LFSR 16b
u<p ? +1:−1
Spin out
1 bit
block-parallel
provenance

Chain of custody

All randomness here is intentional and seeded — any other nondeterminism is a bug. A stochastic sampler is only verifiable if the only thing that varies is the thing you asked to vary: same seed in, byte-identical result out, every time. The record below is the exact provenance of every number on this page, and the receipt is downloadable.

C Run record & receipt

    

    

      
D Raw numbers — top states by probability

      
Every value below is what produced the metrics above — nothing summarized away.

      

        

          statebitsexact Psampled Pcountresidual
        

      

    

  


  
  
acceptance test
Score a device's samples

  

    
E Device-under-test ingest — the hardware slot

    
This is where real hardware plugs in. Paste a sample stream
      (state indices 0–255, any separators) from an RTL sim, an emulator, or — with access —
      the TSU itself, and the harness scores it against the exact reference: pass/fail, distribution
      distance, and per-spin marginals showing where it deviates. 
      (Exact ground truth is enumerable here because the model is small. At scale you can't enumerate 2^N —
      you verify the same way on marginals and the conditional P(sᵢ=+1 | field)=σ(2βf); same harness.)

    
    

      
      
      
      
    

    

  


  

    

      
What this is

      
Thermodynamic hardware computes by sampling a Boltzmann distribution in silicon.
        Before you can trust the chip you need a bit-accurate software oracle to check it against, plus a study
        of how much datapath precision the sampling actually needs. This is that oracle: fixed-point field MAC,
        sigmoid LUT, LFSR compare and block-Gibbs update, each modeled as an FPGA/ASIC builds it, scored against
        the brute-force-enumerated true distribution — and everything is reproducible from the seed.

    

    

      
Read it like a verification engineer

      
Drop the fractional bits to ~2 and the sampler produces garbage. Cut the LUT below 5
        address bits (interpolation off) and the sigmoid biases every conditional. The headline: this model
        samples the correct Boltzmann distribution with only a Q_.6 field, a 32-entry interpolated sigmoid
        LUT, and a 16-bit LFSR — a minimum spec that is an area/power number, derived not guessed. The
        same LUT and LFSR drive a synthesizable Verilog core that passes 12,864/12,864 self-checking
        vectors in Icarus Verilog.